Pushing the Limits: Dual GH200 Hits 10k tok/s Prefill for DeepSeek-V4-Flash with 1M Context
A breakthrough in LLM inference has been achieved on dual NVIDIA GH200 Grace Hopper Superchips. By leveraging the DSV4-specific cache layout patch (PR #48993) and SGLang optimizations, developers reached a staggering 10,000 tok/s prefill (PP) rate and over 300 tok/s token generation (TG) throughput, enabling a 1-million-token context window within 192GB of HBM.
- ▶ Low-Level Cache Engineering: The integration of specialized DSV4 cache layouts is the “secret sauce” that minimizes memory fragmentation, allowing the 192GB HBM footprint to sustain massive context windows that were previously unreachable.
- ▶ ARM64/GH200 Synergy: Successful deployment on ARM64 underscores a strategic shift; specialized silicon paired with an optimized runtime (SGLang) is outperforming traditional x86/GPU clusters in long-context efficiency.
- ▶ Speculative Gains: By configuring DSpark for 6-token lookahead and disabling asynchronous scheduling, the setup effectively bypassed standard bottlenecking, pushing generation speeds to the 300 tok/s frontier.
Bagua Insight
This isn’t just a benchmark victory; it’s a validation of “Model-Aware Inference.” As models like DeepSeek deviate from standard Transformer architectures, the performance bottleneck shifts from raw TFLOPS to sophisticated memory orchestration. Hitting 10k tok/s prefill effectively kills the “latency wall” in RAG pipelines, making real-time analysis of entire libraries feasible. The success on ARM64 further signals that the future of high-throughput inference belongs to high-bandwidth, unified memory architectures like Grace-Hopper, which can handle the massive KV cache demands of GenAI better than legacy PCIe-bound systems.
Actionable Advice
Infrastructure leads should pivot from generic GPU scaling to memory-centric architectures for long-form GenAI. Monitoring bleeding-edge PRs in the vLLM/SGLang ecosystem—specifically those targeting MoE memory management—is no longer optional; it is the primary lever for maintaining a competitive TCO. For RAG-heavy workloads, prioritize hardware with unified memory structures to maximize the utility of specialized model kernels.